1. Field of the Invention
The present invention relates to a structure of a memory cell of a memory cell array incorporated in a semiconductor device such as a dynamic semiconductor memory device and the like which are widely employed as a memory in personal computers, IC card and the like. More particularly, the present invention is concerned with an improved memory cell structure of a memory cell array which can effectively suppress leakage of electrical charge stored in a charge storing capacitor constituting a part of the memory cell.
2. Description of Related Art
The dynamic semiconductor memory device as mentioned above is widely used as a memory device for personal computers, IC cards and the like. For better understanding of the present invention, its technical background will be described in some detail by reference to the drawings.
FIG. 7 is a block diagram showing a typical electrical circuit configuration of a dynamic memory device known heretofore. Referring to FIG. 7, the illustrated dynamic memory device is implemented in such a structure as explained below. Address input signals A0 to A9 applied to address input terminals from a central processing unit or CPU (not shown) are temporarily stored in a row and column address buffer 1 and outputted therefrom to a row decoder 5 and a column decoder 7, respectively, under the timing of a clock signal generated by a clock generator 3, whereby store locations, i.e., the locations determined by the row addresses and the column addresses of the memory cell array 9 at which the data are to be stored, are determined. In that case, the data input through the data input terminals are temporarily stored in an input data buffer 11 before being stored in the store locations of the memory cell array 9, determined as mentioned above, after amplification by a sense refresh amplifier 13 in synchronism with a clock signal generated by the clock generator 3 so long as no write signal is input. On the other hand, operation for reading out the data from the memory cell array 9 is performed under the timing of a clock signal generated by the clock generator 3 via the sense refresh amplifier 13 to be subsequently stored temporarily in an output data buffer 15, wherein the data held in the output data buffer 15 are output to data output terminals under the timing of a relevant clock signal generated by the clock generator 3 during a period in which no write signal is applied.
FIG. 8 is an enlarged sectional view showing fragmentarily a physical structure of the memory cell array 9. As can be seen in the figure, each of the memory cells of the memory cell array 9 is composed of a charge storing capacitor generally denoted by a reference numeral 101 and having an upper electrode portion 101a and a lower electrode portion 101b, an MOS transistor generally denoted by a numeral 103 for controlling storage and release of charge in and from the capacitor 101 (i.e., data write and read operations), and a contact region 105 for electrically connecting the lower electrode portion 101b of the capacitor 101 and a source region 109 of the MOS transistor 103 to each other.
Each of the MOS transistors 103 is comprised of the source region 109 mentioned above and a drain region 111 both formed in a substrate 107 and a gate region 113 for controlling the state of conduction between the source region 109 and the drain region 111, wherein a gate insulation oxide film 113a is interposed between a bottom surface of the gate region 113 and a top surface of the substrate 107, while both lateral surfaces and the top surface of each gate region 113 are covered with an insulation film 113b. Further, bit wires 115 serving for transmission of information or data read out from the memory cell to the sense amplifier as well as transmission of data to be written in the memory cell are deposited over and across the gate regions 113 of the adjacent memory cells and the drain regions 111 disposed therebetween, respectively.
FIG. 9 is a partially enlarged view of FIG. 8 showing in more detail a fragment of the memory cell array 9, and FIG. 10 is a circuit diagram showing an equivalent circuit thereof. In FIG. 10, a reference numeral 117 denotes a word wire connected to the gate 113 for controlling the on/off state thereof.
In the memory cell array 9 realized in the structure described above, the gate 113 is opened or closed (i.e., controlled to be off or on) by the signal on the word wire 117 to thereby turn off or on the MOS transistor 103. In this way, the capacitor 101 can be charged or discharged in response to the signal on the bit wire 115.
As will be appreciated by examining in FIGS. 9 and 10, the electrical charge stored or accumulated in the capacitor 101 of each of the memory cells is likely to leak through a boundary defined between the source region 109 and the substrate 107 via the contact 105 even when the MOS transistor 103 is in the nonconducting state, incurring a corresponding decrease of charge stored in the capacitor 101. The leakage current thus generated is primarily composed of a leakage current component a flowing to the drain 111 via the gate 113, a leakage current component b flowing from an upper edge portion of the source region 109 to the substrate 107, a leakage current component c flowing from a location close to a contact region between the source region 109 and a LOCOS (LOCalized Oxidation of Silicon) region 119 to the substrate 107, and a leakage current component d flowing outwardly through the source region 109 from the other porion of the boundary defined between the source region 109 and the substrate 107.
As the causes for generation of the leakage current components mentioned above, there may be conceived damage which the boundary surface of the source region 109 (inter alia, the edge regions located at both sides of the source region 109) may undergo during etching, sputtering and other processes in the course of manufacturing of the semiconductor memory device, stress applied to the boundary between the source region 109 and the LOCOS region 119 during a thermal process for forming the LOCOS region 119, an electric-field ascribable stress applied in the ordinary operation and others. In this conjunction, it should be mentioned that the leakage current components b and c are usually greater than the leakage current components a and d.
FIG. 11 is a timing chart illustrating operations performed on the capacitor of the memory cell. In the figure, a voltage appearing acrose the capacitor is taken along the ordinate with the time being taken along the abscissa, wherein a curve shown at (A) represents the voltage applied across the capacitor, a curve shown at (B) represents a voltage appearing across a capacitoe in the memory cell of the memory cell array 9 known heretofore, and a curve shown at (C) represents a capacitor voltage of the memory cell in a memory cell array realized according to the teachings of the present invention, as will be described later on.
Now, operation of the hitherto known memory cell 9 will be explained by reference to FIGS. 7, 10 and 11. Assuming that a write signal of high level is applied to the gate 113 from the word wire 117 at a time point t1, the gate 113 is turned on, whereby the MOS transistor 103 is switched to the conducting state (i.e., "ON" state), which results in a current flow through the MOS transistor 103 from the bit wire 115. As a consequence, a voltage of a corresponding level is applied across the capacitor 101 which is thus charged up to a saturated state or level. At a time point t2, the write signal applied to the gate 113 from the word wire 117 is switched to a low level. However, the capacitor 101 is maintained in the saturated state until the MOS transistor 103 becomes nonconducting. At this time point t2, the supply of the charge to the capacitor 101 is interrupted, and the charge stored in the capacitor 101 leaks to the substrate 107 by way of the contact region 105 and the source region 109, as described previously in conjunction with FIG. 9. Thus, the voltage appearing across the capacitor 101 decreases gradually. When the voltage of the capacitor 101 decreases from the predetermined voltage level to such a level at which the data stored or memorized in terms of a quantity of charge cannot be restored even when the refresh operation known per se is performed, the data as stored will be lost. Accordingly, before the voltage of the capacitor 101 falls below the predetermined value, the capacitor 101 has to be charged to the saturated state via the sense refresh amplifier 13 in synchronism with a clock signal generated periodically at a predetermined time interval (e.g. at t3). This is what is called the refresh operation.
FIG. 12 is a view graphically illustrating changes in fail bit numbers as a function of time lapse due to the leakage currents in memory cell arrays which have a predetermined memory capacity (e.g. 1M bytes) and which differ from one another in respect to the charge storing capacity of the individual memory cells. In this figure, the fail bit number is taken along the ordinate while the time lapsing from the time point at which the MOS transistor 103 is turned off (i.e., switched to the nonconducting state) is taken along the abscissa in milliseconds. Further, in FIG. 12, curves (a), (b) and (c) represent changes in the fail bit number in the memory cell arrays of which memory cells have small, medium and large charge storing capacities, respectively, whereas a curve (d) represents the change in the fail bit number in a memory cell array realized according to the teachings of the present invention which will be described hereinafter and having a same storage capacity as the memory cell array represented by the curve (a).
As can be seen from FIG. 12, in the conventional memory cell array 9, the charge storing capacity of the individual memory cells, i.e., that of the capacitor 101, will have to be increased in order to decrease the fail bit number and hence the ratio of the leakage current to the charge storing capacity of the memory cell. This in turn means that the refreshing time interval will have to be shortened to a value on the order of 10 ms, as adopted commonly in the conventional dynamic semiconductor memory devices.
With the memory cell structure of the semiconductor memory device known heretofore in which each memory cell is composed of one MOS transistor 103 and one charge storing capacitor 101 and in which the lower electrode 101b of the capacitor 101 is directly connected to the source region 109 of the MOS transistor 103 via the contact region 105 having a high electrical conductivity (or low resistance, to say in another way), the charge stored in the capacitor 101 decreases at a relatively high rate (i.e., within a relatively short time) due to leakage of the charge via the contact 105 of a low ohmic resistance and the boundary or junction between the source region 109 and the substrate 107 to the substrate 107, which causes the charge or data holding or memorizing capability of the memory cell array 9 to be remarkably lowered, giving rise to a problem.
Under the circumstances, in order to hold unchangeably the data stored at each memory cell without fail, the individual memory cells have to be refreshed at a relatively short time interval or alternative the charge storing capacity of the memory cell has to be increased in order to decrease the ratio of leakage of the charge to the charge storing capacity of the memory cell. However, the refreshing operations executed at a relatively short time interval provide a great obstacle to realization of high-speed operation of the memory cell array 9. On the other hand, increasing of the charge storing capacity of the individual memory cells incurs not only a correspondingly increased cell size but also an increase in power consumption, another disadvantage.